Chihiro Yoshimura, Masanao Yamaoka, Hidetaka Aoki, and Hiroyuki Mizuno,“Spatial computing architecture using randomness of memory cell stability under voltage control ,”21st European Conference on Circuit Theory and Design (ECCTD 2013), September 2013. https://ieeexplore.ieee.org/abstract/document/6662276/
Masanao Yamaoka, Chihiro Yoshimura, Masato Hayashi, Takuya Okuyama, Hidetaka Aoki, and Hiroyuki Mizuno, “20k-spin Ising chip for combinational optimization problem with CMOS annealing,” IEEE International Solid-State Circuits Conference (ISSCC 2015), February 2015.
Masanao Yamaoka, Chihiro Yoshimura, Masato Hayashi, Takuya Okuyama, Hidetaka Aoki, Hiroyuki Mizuno, “A 20k-spin Ising chip to solve combinatorial optimization problems with CMOS annealing ,” IEEE Journal of Solid-State Circuits, 303 – 309, 09 December 2015. https://ieeexplore.ieee.org/abstract/document/7350099/
Masato Hayashi, Masanao Yamaoka, Chihiro Yoshimura, Takuya Okuyama, Hidetaka Aoki, and Hiroyuki Mizuno, “An accelerator chip for ground-state search of the Ising model with asynchronous random pulse distribution,” 6th International Workshop on Advances in Networking and Computing (WANC’15), December 2015.
Takuya Okuyama , Masato Hayashi , Masanao Yamaoka, “An Ising Computer Based on Simulated Quantum Annealing by Path Integral Monte Carlo Method,” 2017 IEEE International Conference on Rebooting Computing (ICRC),8-9 Nov. 2017. https://ieeexplore.ieee.org/abstract/document/8123652/