About CMOS Annealing Machine
The CMOS annealing machine is a dedicated computer for efficiently solving combinatorial optimization problems.
In order to deal with various types of combinatorial optimization problems, the CMOS annealing machine uses a mathematical model generally seen in the field of statistical mechanics called the Ising model. And because the machine uses specialized hardware, the complex problems can be solved extremely efficiently.
Several methods are developed internally and externally as hardware suitable for the calculation of the Ising model.
CMOS annealing is available in (1) ASIC and (2) FPGA versions based on CMOS circuit technology, a widely used semiconductor technology, and (3) GPU-enhanced versions that implement algorithms for fully connected problems. The ASIC and FPGA versions offer the advantages of high scalability and miniaturization, while the GPU-enhanced versions are capable of dealing with the fully connected problem, making them suitable for different applications and purposes.
There are two kinds of implementations as CMOS annealing machines.
(1) ASIC version
Processing 147,456 spins (equivalent to 384x384 King's Graph) with one annealing
(2) FPGA version
Processing 6,400 spins (equivalent to 80x80 King's Graph) with one annealing
(3) GPU (King’s graph) version
Performing the optimization process equivalent to (1) and (2) using GPGPU, capable of processing 256k spins (equivalent to 512x512 King's Graph). Intended applications include further large-scale verification of CMOS annealing machine hardware.
(4) GPU-enhanced version
Processing 250 times faster than conventional techniques by implementing Momentum Annealing, a completely new algorithm for all fully connected problems on GPU.
On this site you can experience the demo app for the current (1)ASIC version implementation.