CMOS annealing is a dedicated combinatorial optimization processing technology
developed by Hitachi.
CMOS annealing machine is a non-Neumann architecture computer that Hitachi has developed by utilizing
the structure of
SRAM, a storage device, to perform optimization processing with the Ising model. Since the first
prototype was released
in 2015, the prototype implemented with ASIC has achieved the world's highest specs, and we also
launched a shift
generation solution with CMOS annealing in 2020.
CMOS annealing machines that run in this cloud service:
(1) ASIC version
Can process 147,456 spins (equivalent to a 384x384 King's graph) in a single annealing.
(2) GPU (King's graph) version
Can process 256k spins (equivalent to 512x512 King's graph) using GPGPU.
Intended for verifying the further increase in the scale of dedicated CMOS annealing machine hardware
such as the ASIC
CMOS Annealing Machine
Processing combinatorial optimization problems with the annealing method is not especially new; it
has been done for a long time to varying results.
Normally, combinatorial optimization processing is performed by executing a program that performs
annealing on a von Neumann computer. But in order to gain the high speed and low power consumption of
annealing, dedicated hardware needed to be conceived and developed.
The CMOS annealing machine is unique in that it is strictly a non-von Neumann computer. It's unique
feature is that it is able to transfer directly data from SRAM directly to calculations. It was
developed by Masanao Yamaoka of Hitachi, Ltd. in 2015 and was announced at ISSCC 2015 which is called
the Olympics of semiconductor integrated circuit. (Masanao Yamaoka, et al. "20k-spin Ising chip
for combinational optimization problem with CMOS annealing," IEEE International Solid-State Circuits
Conference (ISSCC 2015), February 2015.)
In addition to CMOS annealing machines, dedicated hardware for combinatorial optimization problems
are being rapidly developed and manufactured, some examples include: the quantum annealing machine by
D-Wave Systems in Canada, coherent Ising machine of ImPACT, digital annealer of Fujitsu Laboratories
and more. As detailed here, new technologies to process
combinatorial optimization problems at a high speed are indispensable for improving IoT society in the
future, and we need to move quickly.
Among the various combinatorial optimization dedicated hardware, the most appealing feature of the
CMOS annealing machine is the low power consumption, excellence in scalability, and the possiblility
of downsizing equipment.
Because CMOS annealing machines are based on widely used semiconductor technology, they are made with
small chips and there are no special restrictions on their operating environment. It can also be
embedded in our daily living space. This has important implications in information processing in the
In addition, all of the hardware listed above have the ability to express combinatorial optimization
problems to be solved in the Ising model. The larger the number of spins that make up the Ising model,
the larger the scale of problems that can be handled, meaning hardware that can support more spin
numbers will always be required.
CMOS integrated circuit technology has the highest degree of integration among the technologies used
and we use CMOS annealing for its high integration. In addition, CMOS annealing also provides a
mechanism for connecting multiple chips, even if a problem is too large scale to be handled directly
with the number of spins mounted on a single chip, by connecting multiple chips, the problem can be
solved with the power of high scalability.
Operating principle of CMOS annealing machine
CMOS annealing is a technology to achieve the annealing operation using CMOS integrated circuits.
In order to realize CMOS annealing, it is necessary to have two actions "a means of moving toward
lower energy" and "a means to escape from the local solution" as shown in the figure below.
"Means of moving in a direction of low energy" is a deterministic motion that transitions the state
to a state of low energy according to the energy landscape.
With only deterministic behavior, it is trapped in the locally existing energy valleys called local
solutions, making it difficult to explore further lower energy states. Therefore, in order to escape
from this local solution, the state of energy is randomly changed by probabilistic motion, and search
the state of energy as low as possible.
We call an operation "CMOS annealing" that searches for a low energy state by combining these two
operations on the memory cell array simulating the structure of the Ising model.
Correspondence between Ising model and memory cell array
Realization of base search state
Mapping of combinatorial optimization problem
For a method of mapping combinatorial optimization problem to Ising model, please read tutorials on
this website and Fixstars' quantum computer
information website .