We have shown that it could grow indefinitely as long as the boards are connected. We will be able to meet customers’ demand for larger scale.
Two years after the announcement of the business-card-sized prototype, as a result of the
NEDO project, we announced a
new CMOS annealing machine that can handle 144k spins by connecting 9 CMOS annealing chips
vertically, horizontally, and
diagonally. It shows that it can be infinitely enlarged in two dimensions by connecting
them. The machine can be
connected to an infinite number of chips in two dimensions, hoping to meet the demand for
even larger scales in the
This is the ASIC version of the annealing machine implemented and serviced by this cloud service.
We have implemented an environment to run the annealing of an ASIC version of the CMOS
annealing machine as software on
a GPU, supporting 256k spins and having a 32-bit coefficient width. It supports 256k spins
and has a 32-bit coefficient
width. We aim to accelerate the exploration of applications by testing problems that
cannot be solved in hardware.
This is the GPU (King's graph) version of the annealing machine implemented and serviced by this cloud service.
We presented an algorithm for ground-state search of the all-coupled Ising model. We implemented it on a GPU and proved to be 250 times faster than the conventional optimized SA method.More...
In a NEDO project started in 2016, Hitachi had been working on developing a large-scale CMOS annealing machine, and created a prototype that operates by connecting two chips together. The result turned out to be the world's smallest hardware. It ended up being just as small as a business card, but the annealing machine can handle 30,976 x 2 = 61,952 spins, consumes less energy, and operates over a USB connection. We have also shown that it can be embedded in edge devices.
In 2018, we successfully connected 25 FPGAs to operate as a single CMOS annealing machine. This enabled the hardware to handle a large scale combinatorial optimization problem with 102,400 spins. Expanding on this achievement, later ASIC prototypes were extended by connecting the chips. We have shown that scalable computation can be achieved by computing digitally.
We implemented the second-generation prototype which was released in 2016 in an FPGA. By sharing the processing of parameters among multiple elements, we were able to reduce the circuitry to 1/10 size of the previous prototype in the same machine area, while also improving the computational accuracy. The programmable prototype has further accelerated the research and development of subsequent CMOS annealing machines.
We presented a CMOS annealing machine that is the world's first ising machine implemented in semiconductor CMOS and operating at room temperature.