The cloud platform for developing applications for quantum annealing and Ising machines
Compatible with Hitachi CMOS annealing machine, Fixstars GPU annealing machine "Fixstars Amplify Annealing Engine"
and other major quantum annealing and Ising machines
The experiential learning application for Ising machines
Compatible with Hitachi CMOS annealing machine, Fixstars GPU annealing machine "Fixstars Amplify Annealing Engine"
and other major quantum annealing and Ising machines
CMOS Annealing machine official links from Hitachi
Chihiro Yoshimura, Masanao Yamaoka, Hidetaka Aoki, and Hiroyuki Mizuno,"Spatial computing architecture using randomness of memory cell stability under voltage control ,"21st European Conference on Circuit Theory and Design (ECCTD 2013), September 2013. https://ieeexplore.ieee.org/abstract/document/6662276/
Masanao Yamaoka, Chihiro Yoshimura, Masato Hayashi, Takuya Okuyama, Hidetaka Aoki, and Hiroyuki Mizuno, "20k-spin Ising chip for combinational optimization problem with CMOS annealing," IEEE International Solid-State Circuits Conference (ISSCC 2015), February 2015.
Masanao Yamaoka, Chihiro Yoshimura, Masato Hayashi, Takuya Okuyama, Hidetaka Aoki, Hiroyuki Mizuno, "A 20k-spin Ising chip to solve combinatorial optimization problems with CMOS annealing ," IEEE Journal of Solid-State Circuits, 303 - 309, 09 December 2015. https://ieeexplore.ieee.org/abstract/document/7350099/
Masato Hayashi, Masanao Yamaoka, Chihiro Yoshimura, Takuya Okuyama, Hidetaka Aoki, and Hiroyuki Mizuno, "An accelerator chip for ground-state search of the Ising model with asynchronous random pulse distribution," 6th International Workshop on Advances in Networking and Computing (WANC'15), December 2015.
Masato Hayashi, Masanao Yamaoka, Chihiro Yoshimura, Takuya Okuyama, Hidetaka Aoki, and Hiroyuki Mizuno, "Accelerator Chip for Ground-state Searches of Ising Model with Asynchronous Random Pulse Distribution," International Journal of Networking and Computing ,ISSN 2185-2839 (print), ISSN 2185-2847 (online),Volume 6, Number 2, pages 195-211, July 2016. https://www.jstage.jst.go.jp/article/ijnc/6/2/6_195/_article/-char/ja#article-overiew-abstract-wrap
Takuya Okuyama, Chihiro Yoshimura, Masato Hayashi, Masanao Yamaoka, "Computing architecture to perform approximated simulated annealing for Ising models ," 2016 IEEE International Conference on Rebooting Computing (ICRC), 10 November 2016. https://ieeexplore.ieee.org/abstract/document/7738673/
Masanao Yamaoka, "New-paradigm CMOS Ising computing for combinatorial optimization problems," 2017 IEEE Electron Devices Technology and Manufacturing Conference (EDTM) Date of Conference,28 Feb.-2 March 2017. https://ieeexplore.ieee.org/abstract/document/7947502/
Masanao Yamaoka,"An ising computing to solve combinatorial optimization problems,"
2017 Fifth Berkeley Symposium on Energy Efficient Electronic Systems & Steep Transistors Workshop (E3S),19-20 Oct. 2017.
https://ieeexplore.ieee.org/abstract/document/8246195/
Takuya Okuyama , Masato Hayashi , Masanao Yamaoka, "An Ising Computer Based on Simulated Quantum Annealing by Path Integral Monte Carlo Method," 2017 IEEE International Conference on Rebooting Computing (ICRC),8-9 Nov. 2017. https://ieeexplore.ieee.org/abstract/document/8123652/
Chihiro Yoshimura, Masato Hayashi, Takuya Okuyama, Masanao Yamaoka, "Implementation and Evaluation of FPGA-based Annealing Processor for Ising Model by use of Resource Sharing," International Journal of Networking and Computing, vol.7, no.2, pp.154-172, 2017. https://www.jstage.jst.go.jp/article/ijnc/7/2/7_154/_article/-char/ja/
Kotaro Terada , Daisuke Oku , Sho Kanamaru , Shu Tanaka , Masato Hayashi , Masanao Yamaoka , Masao Yanagisawa , Nozomu Togawa, "An Ising model mapping to solve rectangle packing problem," 2018 International Symposium on VLSI Design, Automation and Test (VLSI-DAT),16-19 April 2018. https://ieeexplore.ieee.org/abstract/document/8373233/
Yamaoka, Masanao, "A CMOS Annealing Machine to Solve Combinatorial Optimization Problems," IEICE ESS Fundamentals Review, vol. 11, issue 3, pp. 164-171. http://adsabs.harvard.edu/abs/2018ESSFR..11..164Y
T. Takemoto, M. Hayashi, C. Yoshimura, M. Yamaoka, “A 2×30k-Spin Multichip Scalable Annealing Processor Based on a Processing-In-Memory Approach for Solving Large-Scale Combinatorial Optimization Problems”, IEEE International Solid-State Circuits Conference (ISSCC 2019), February 2019. https://ieeexplore.ieee.org/document/8662517
T. Takemoto, K. Yamamoto, C. Yoshimura, M. Hayashi, M. Tada, H. Saito, M. Mashimo, M. Yamaoka, “144Kb Annealing System Composed of 9×16Kb Annealing Processor Chips with Scalable Chip-to-Chip Connections for Large-Scale Combinatorial Optimization Problems”, IEEE International Solid-State Circuits Conference (ISSCC 2021), February 2021.
